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In this role, you will work on the design, development, and refinement of Multi-Gbps NRZ & PAM4 SERDES IP. You will be part of a growing analog and mixed signal R&D team developing high speed analog integrated circuits in the world’s most advanced technologies. Working from SERDES standards to block specifications, you quickly identify potential circuit architectures and successful design strategies. You will work with a cross functional design team of analog and digital designers from a wide variety of backgrounds. Our environment is best in class with a full suite of IC design tools supplemented by custom, in-house tools supported by an experienced software/CAD team.
Job Responsibility:
Review SERDES standards to develop novel transceiver architectures and sub-block specifications
Investigate and develop circuit architectures that address architectural bottlenecks and lead to revolutionary improvements in power, area, and performance targets
Oversee physical layout to minimize the effect of parasitics, device stress, and process variation
Present and review simulation data from internal project teams
Document design features and test plans
Consult on the overall electrical characterization of the SERDES IP product. Review customer silicon data for design enhancements. Propose solutions for post-silicon design updates
Requirements:
Ph.D., M.Sc. with 3+ years, or B.Sc. with 5+ years of practical analog IC design experience
degree in Electrical Engineering or Computer Engineering or other relevant field of study
In depth familiarity with transistor level circuit design - sound CMOS design fundamentals
Detailed design experience with one, and familiarity with several other SERDES sub-circuits: receive equalizers, samplers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillator, phase mixer, delay-locked loop, phase locked loop, bandgap reference, ADC, DAC
Familiarity with custom digital design (i.e. high-speed logic paths)
Experience with analog/digital interactions for optimizing circuit performance (calibration, adaptation, timing-handoff, etc)
Understanding of design for reliability (i.e. EM, IR, aging, etc.) and layout effects (i.e. matching, reliability, proximity effects, etc.) as well as ESD issues (i.e. circuit techniques, layout)
Experience with tools for schematic entry, physical layout, and design verification
Understanding of SPICE simulators and simulation methods
Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture
Excellent communication, presentation, and documentation skills
Nice to have:
Experience with TCL, Perl, C, Python, MATLAB, or other scripting languages is desired
What we offer:
Comprehensive medical and healthcare plans
Time Away in addition to company holidays, ETO and FTO Programs
Family Support including maternity and paternity leave, parenting resources, adoption and surrogacy assistance
ESPP - Purchase Synopsys common stock at a 15% discount