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Teradyne’s Semiconductor Test Division at our Agoura Hills, CA facility is looking for an intern to partner with our engineers and participate in the design of high-speed (> 1 Gbps) ICs or high-power, high-voltage ICs for ATE (Automatic Test Equipment) instruments. As part of this team, they will assist design engineers in developing specifications for analog blocks. You will be a key in assisting design engineers to optimize and characterize a circuit via simulation (with Cadence EDA tools) over all process and operating conditions. Additionally, the selected intern will take part in the Physical implementation (layout) of circuits, participate in documentation, plus be part of the design review as well as participate in IC evaluation in the lab. This is a summer intern on-site at our headquarters in Agoura Hills, CA.
Job Responsibility:
Assist design engineers in developing specifications for analog blocks
Assist design engineers to optimize and characterize a circuit via simulation (with Cadence EDA tools) over all process and operating conditions
Take part in the Physical implementation (layout) of circuits
Participate in documentation
Be part of the design review
Participate in IC evaluation in the lab
Requirements:
Currently working towards their BSEE/MSEE degree with emphasis on mixed-signal and analog integrated circuit design
Analog and/or Mixed-Signal integrated circuit design knowledge
Cadence EDA tools, Spectre, Hspice
Programming and Scripting, C++, VBA, Python
Knowledge working with lab equipment - oscilloscopes, DMM, etc.
Excellent written and verbal communication skills
Detail-oriented and possess excellent follow-up skills
Ability to work independently with minimal direction
Must be available for a min of 3 months Summer 2026
Nice to have:
Previous industry experience or academic experience with several design tapeouts is a plus