CrawlJobs Logo

AI Silicon Physical Design Engineer

cerebras.net Logo

Cerebras Systems

Location Icon

Location:
United States , Sunnyvale

Category Icon
Category:
IT - Software Development

Job Type Icon

Contract Type:
Not provided

Salary Icon

Salary:

150000.00 - 250000.00 USD / Year
Save Job
Save Icon
Apply Position

Job Description:

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs.

Job Responsibility:

  • Excelling in synthesizing, placing, and routing high speed designs.
  • Experiencing the full spectrum of physical design and implementation.
  • Collaborating closely with the RTL team.
  • Integrating blocks seamlessly into the full-chip architecture.

Requirements:

  • 10+ years of physical design & physical verification experience.
  • Strong knowledge of block level and full-chip physical verification methodology.
  • Strong experience in block/subsystem timing closure.
  • Expert at optimizing for the best power/performance and area.
  • Experience with the complete physical design flow.
  • Expert with ICV or Calibre tools resolving block and full-chip DRC and LVS issues.
  • Expert with IR/EM analysis and resolution.
  • Good understanding of full chip floor planning and integration.
  • Strong ability in scripting languages like Tcl and Python. Ability to make flow enhancements.
  • Demonstrated ability to work with RTL teams to optimize for physical design.
  • Skills in Design Compiler, Fusion Compiler, ICC2 or similar physical design tools.
  • BS or MS in Electrical Engineering.

Nice to have:

  • Knowledge of Synopsys tool suite is a plus.
  • Knowledge of CPU/GPU design a plus.
What we offer:
  • Build a breakthrough AI platform beyond the constraints of the GPU.
  • Publish and open source their cutting-edge AI research.
  • Work on one of the fastest AI supercomputers in the world.
  • Enjoy job stability with startup vitality.
  • Simple, non-corporate work culture that respects individual beliefs.

Additional Information:

Job Posted:
February 17, 2026

Employment Type:
Fulltime
Work Type:
Remote work
Icon
Cerebras Systems - All Job Offers
Job Link Share:
Copy Link Icon
Facebook Icon Twitter Icon LinkedIn Icon
PREMIUM
More languages and countries
+ Unlock 31694 hidden job offers
Languages
English Čeština Deutsch Ελληνικά Español Français +15
Countries
United States United Kingdom India Canada Australia +
See plans
Plans from $2.99 / month

Looking for more opportunities? Search for other job offers that match your skills and interests.

Briefcase Icon

Similar Jobs for AI Silicon Physical Design Engineer

Principal Silicon Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...
Location
Location
United States , Mountain View
Salary
Salary:
139900.00 - 274800.00 USD / Year
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience
  • Ability to meet Microsoft, customer and/or government security screening requirements
  • Ability to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
  • Provide proof of country of citizenship or proof of US residency or other protected status for export control assessment
  • Bachelor of Science in Electrical or Computer Engineering
  • 8+ years of experience in RTL design and design checks (CDC/RDC/VCLP/LINT)
  • 8+ years of experience in Synthesis, Timing constraints and Power Performance Area (PPA) trade-offs
  • Proficiency in RTL to Physical Design collateral development including timing and synthesis constraints
  • Knowledge of full RTL2GDS flow
  • Hands-on experience with industry tools for synthesis, STA, and PD flows (e.g., PrimeTime, Genus/DC, Innovus/ICC2)
Job Responsibility
Job Responsibility
  • Serve as the middle-engineering technical leader at the intersection of RTL, physical design, and mixed-signal integration for Azure’s custom silicon programs
  • Ensure that design intent—digital and mixed-signal—is captured accurately in constraints, flows, and sign-off methodologies
  • Lead the capture and validation of design intent for digital and mixed-signal blocks, ensuring accurate constraints and seamless integration across front-end and physical design flows
  • Provide static timing leadership for mixed-signal interfaces, driving timing closure, exception quality, and correlation across corners
  • Partner closely with RTL, PD, mixed-signal, DFT, and CAD teams to resolve cross-domain issues and maintain alignment on timing, power, and functional requirements
  • Run, review and debug physical design flows, timing reports, ensuring consistency with synthesis and STA assumptions and driving convergence through targeted mitigations
  • Contribute to design automation including leveraging AI, constraint-checking, and flow improvements that enhance execution efficiency and PPA
  • Operate with limited direction, demonstrating strong ownership, attention to detail, and the ability to communicate clear, data-driven status, risks, and mitigation plans to program leadership
  • Fulltime
Read More
Arrow Right

Principal Physical Design Manager

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...
Location
Location
India , Bangalore
Salary
Salary:
Not provided
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Bachelor's or master’s in electrical or computer engineering or related field with 15+ years of experience
  • Experience in physical design implementation, signoff at block / sub system / sub-chip / SoC level
  • Experience in tapeouts of complex ASICs in leading edge technology
  • Ability to meet Microsoft, customer and/or government security screening requirements
  • This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
  • This role will require access to information that is controlled for export under export control regulations
  • As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status
  • To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport
Job Responsibility
Job Responsibility
  • Lead a team in defining implementation and execution plan for a schip/SOC
  • Execute the plan for successful tapeout by working with various stakeholders (RTL, IP, Methodology, DFT, Architecture etc)
  • Drive the to achieve the best performance, power, and area (PPA) for AI system-on-chips (SOCs)
  • Optimizing technology, libraries, physical design, RTL design, and architecture
  • Leading the team in defining the implementation and execution plan for a subchip/SOC
  • Collaborating with various stakeholders such as RTL designers, IP teams, Methodology experts, DFT engineers, and Architects to ensure a cohesive plan
  • Executing the defined plan to ensure successful tapeout of the subchip/SOC
  • Driving the team to achieve the best performance, power, and area (PPA) for AI system-on-chips
  • Optimizing technology choices, libraries, physical design methodologies, RTL design strategies, and architectural decisions to meet performance targets
  • Ensuring that the physical design aspects align with the overall project goals and timelines
  • Fulltime
Read More
Arrow Right

Principal Physical Design Manager

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...
Location
Location
United States , Raleigh
Salary
Salary:
139900.00 - 274800.00 USD / Year
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
  • Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
  • Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
  • Ability to meet Microsoft, customer and/or government security screening requirements
  • Ability to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
  • Ability to provide proof of country of citizenship or proof of US residency or other protected status for export control assessment
  • Bachelor's or master’s in electrical or computer engineering or related field with 10+ years of experience
  • Experience in physical design implementation, signoff at block / sub system / sub-chip / SoC level
  • Experience in tapeout of complex ASICs in leading edge process node technology
  • 8+ years of hands-on experience in EDA vendor tools such as Fusion Compiler, VCLP, Primetime, Formality, or Cadence Innovus and Conformal
Job Responsibility
Job Responsibility
  • Lead a team in defining implementation and execution plan for a schip/SOC
  • Execute the plan for successful tapeout by working with various stakeholders (RTL, IP, Methodology, DFT, Architecture etc)
  • Drive the team to achieve the best performance, power, and area (PPA) for AI system-on-chips (SOCs)
  • Optimizing technology, libraries, physical design, RTL design, and architecture
  • Collaborate with various stakeholders such as RTL designers, IP teams, Methodology experts, DFT engineers, and Architects
  • Provide technical guidance and mentorship to team members
  • Oversee the development and implementation of physical design flows and methodologies
  • Collaborate with cross-functional teams to address design challenges and optimize for manufacturability
  • Monitor progress, identify risks, and implement mitigation strategies
  • Keep abreast of the latest industry trends, tools, and techniques in physical design
  • Fulltime
Read More
Arrow Right

Physical Design Engineer

This individual contributor role sits within our physical design team and is cen...
Location
Location
United States , San Francisco
Salary
Salary:
266000.00 - 445000.00 USD / Year
openai.com Logo
OpenAI
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • BS w/ 4+ or MS with 2+ or PhD with 0-1 year(s) of relevant industry experience in physical design and methodology development
  • Demonstrated success in taping out complex silicon designs
  • Hands-on experience with block physical implementation and PPA convergence
  • Strong coding experience with python, bazel, TCL
  • Strong experience building physical design tools, flows and methodologies
  • Strong understanding of microarchitecture, RTL design, physical design, circuit design, physical verification and timing closure
  • Deep familiarity with industry-standard tools and flows for physical synthesis, PNR, LEC and power estimation
Job Responsibility
Job Responsibility
  • Develop, build and own tools, flows and methodologies for physical implementation
  • Own physical implementation of floorplan blocks from floorplanning to final signoff
  • Collaborate with RTL designers to drive optimal block implementation solutions
  • Analyze and optimize design for timing, power, and area trade-offs, working in collaboration with EDA vendors and ASIC partners
What we offer
What we offer
  • Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts
  • Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)
  • 401(k) retirement plan with employer match
  • Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)
  • Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees
  • 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)
  • Mental health and wellness support
  • Employer-paid basic life and disability coverage
  • Annual learning and development stipend to fuel your professional growth
  • Daily meals in our offices, and meal delivery credits as eligible
  • Fulltime
Read More
Arrow Right

Pmts Silicon Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING. At AMD, our mission is to build great pro...
Location
Location
India , Hyderabad
Salary
Salary:
Not provided
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • 14–18+ years of semiconductor design experience
  • Strong hands‑on RTL design and microarchitecture ownership, with designs that progressed through PD and tapeout
  • Direct experience working within or closely alongside Physical Design teams
  • Deep understanding of SDC intent, timing, clocking, partitioning, and physical closure trade‑offs
  • Proven ability to resolve PD issues through architectural and RTL‑level solutions, not late physical workarounds
  • Experience driving or contributing to shift‑left initiatives or early physical feasibility analysis
  • Comfort operating as a senior technical authority, making cross‑domain engineering decisions
  • Exposure to AI‑assisted or highly automated design flows is a strong plus
  • Own creation and maintenance of physical‑aware RTL to enable PNR hierarchy, including partitioning, feedthroughs, repeaters, and physical intent insertion
  • Partner with SOC Design to translate logical IP integration into physical‑aware RTL and with IP design team creation digital‑on‑top RTL wrappers for analog IPs
Job Responsibility
Job Responsibility
  • Own Physical Design shift‑left strategy, ensuring PD risks are identified at RTL, SDC, and paper‑floorplan stages
  • Act as chief engineering authority for AI‑assisted and automated PD execution, defining where AI can act autonomously and where human judgment is required
  • Bridge RTL, microarchitecture, and PD, translating early PD findings into architectural and RTL‑level corrective actions
  • Define and enforce PD readiness and quality bars across synthesis, PnR, STA, and physical closure
  • Lead predictive closure and risk management, using early indicators to forecast timing, ECO churn, and execution complexity
  • Govern signoff readiness, ensuring AI‑augmented flows never compromise correctness or confidence
  • Codify execution playbooks and best practices to reduce variability and scale high‑quality PD execution across teams
  • Serve as a trusted technical peer to RTL architects, PD leads, and AI/methodology owners
  • Fulltime
Read More
Arrow Right
New

Principal Quantum Analog Design Lead

As a Principal Quantum Analog Design Lead in the Quantum 1st Party Hardware Appl...
Location
Location
United States , Redmond
Salary
Salary:
139900.00 - 274800.00 USD / Year
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Doctorate in Physics, Engineering, or related field AND 3+ years experience in industry or in a research and development environment
  • OR Master's Degree in Physics, Engineering, or related field AND 6+ years experience in industry or in a research and development environment
  • OR Bachelor's Degree in Physics, Engineering, or related field AND 8+ years experience in industry or in a research and development environment
  • OR equivalent experience
  • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role
  • Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
  • Citizenship & Citizenship Verification: This role will require access to information that is controlled for export under export control regulations
  • Ability to leverage AI tools to drive innovation and efficiency
  • Ability to work in an AI-first environment using modern AI tools to accelerate discovery through hardware development
Job Responsibility
Job Responsibility
  • Coordinate interactions with Quantum Qubit design and Measurement teams to define specifications, architecture, and micro-architecture for Analog IP blocks
  • Own and drive the development of analog IP, including microarchitecture, schematic entry, and verification of complex blocks to meet stringent power, performance, and timing goals
  • Create test plans for verification and post-silicon validation and characterization
  • Design and validate analog blocks in simulation, both pre- and post-layout
  • Drive design reviews, status reports, and schedules to deliver against internal end-to-end milestone quality
  • Coordinate the work of other Analog Designers and Verification teams, audit their output, and provide guidance and direction to deliver high-quality results
  • Develop basic test benches and support verification, Design For Test (DFT), and post-silicon validation activities
  • Collaborate effectively with architects, analog mixed-signal designers, verification engineers, and physical design, DFT, and other front-end design teams
  • Align development methodologies with wider teams and drive continuous improvement to Analog Design Flow and development processes for at-scale execution
  • Fulltime
Read More
Arrow Right

Senior Quantum Foundry Technologist & Library Specialist

At Microsoft Quantum, we aim to empower science and scientists to solve the worl...
Location
Location
United States , Redmond
Salary
Salary:
119800.00 - 258000.00 USD / Year
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Doctorate in Physics, Engineering, or related field AND 1+ year(s) experience in industry or in a research and development environment, could include completion of a post doctoral research position
  • OR Master's Degree in Physics, Engineering, or related field AND 4+ years experience in industry or in a research and development environment
  • OR Bachelor's Degree in Physics, Engineering, or related field AND 6+ years experience in industry or in a research and development environment
  • OR equivalent experience
  • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role
  • Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
  • Citizenship & Citizenship Verification: This role will require access to information that is controlled for export under export control regulations
  • As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their U.S. permanent residency or other protected status for assessment of eligibility to access the export-controlled information
  • Doctorate in Physics, Engineering, or related field AND 3+ years experience in industry or in a research and development environment, could include completion of a post doctoral research position
  • OR Master's Degree in Physics, Engineering, or related field AND 6+ years experience in industry or in a research and development environment
Job Responsibility
Job Responsibility
  • Audit external foundries to find a suitable partner for long-term engagement for Microsoft quantum/cryo silicon programs
  • Evaluate their solutions for materials/process tailoring to match our needs
  • Create long-term evolution plans with vendors for evolving process needs for future quantum products
  • Lead technical interactions with external foundries both in pre-silicon design and post silicon development as well as continuous improvement for Yield and performance during production manufacturing stage to ensure Best-in-class Microsoft first-party silicon
  • Find / define design development libraries and re-characterizations for standard cells and analog design PDKs at cryo temperatures
  • Define and design engineering structure in testchip for technology interception and enablement including data collection, analysis and model-silicon characterization
  • Compile and analyze data using common statistical techniques and effectively present key results along with recommended actions
  • practice continuous improvement and yield optimization and analyze products to ensure manufacturability and data sheet compliance
  • Embody our culture and values
  • Fulltime
Read More
Arrow Right
New

Principal Quantum Design Verification Engineer

At Microsoft Quantum, we aim to empower science and scientists to solve the worl...
Location
Location
United States , Redmond
Salary
Salary:
139900.00 - 274800.00 USD / Year
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Doctorate in Physics, Engineering, or related field AND 3+ years experience in industry or in a research and development environment
  • OR Master's Degree in Physics, Engineering, or related field AND 6+ years experience in industry or in a research and development environment
  • OR Bachelor's Degree in Physics, Engineering, or related field AND 8+ years experience in industry or in a research and development environment
  • OR equivalent experience
  • Ability to meet Microsoft, customer and/or government security screening requirements
  • Microsoft Cloud Background Check
  • Citizenship & Citizenship Verification
  • Ability to leverage AI tools to drive innovation and efficiency
  • Ability to work in an 'AI-first' environment using modern AI tools to accelerate discovery through hardware development
Job Responsibility
Job Responsibility
  • Own verification environments and tests for IP and SoC designs, and validate designs in simulation with both pre- and post-layout Register-Transfer Level (RTL) and netlists
  • Coordinate the execution of contingent staff and external vendors to ensure verification deliverables meet specification and schedule
  • Set up and manage databases and flows for SoC and IP repositories
  • set up bug-tracking systems and log, track, manage, and close bugs and issues
  • drive milestone reviews and status reports
  • Create test plans for pre-silicon simulation verification across both digital and analog components, including the development of Analog Mixed-Signal (AMS) simulation models
  • Collaborate with the Design For Test (DFT) team to test DFT features
  • Align verification methodologies with wider teams and drive continuous improvement to Design Verification processes for at-scale execution
  • Collaborate effectively with architects, analog mixed-signal designers, verification engineers, and physical design, DFT, and other front-end design teams
  • Embody our culture and values
  • Fulltime
Read More
Arrow Right