AI Silicon Physical Design Engineer Job at Cerebras Systems (Sunnyvale)

Principal Silicon Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Mountain View

Salary:

139900.00 - 274800.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements
Ability to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
Provide proof of country of citizenship or proof of US residency or other protected status for export control assessment
Bachelor of Science in Electrical or Computer Engineering
8+ years of experience in RTL design and design checks (CDC/RDC/VCLP/LINT)
8+ years of experience in Synthesis, Timing constraints and Power Performance Area (PPA) trade-offs
Proficiency in RTL to Physical Design collateral development including timing and synthesis constraints
Knowledge of full RTL2GDS flow
Hands-on experience with industry tools for synthesis, STA, and PD flows (e.g., PrimeTime, Genus/DC, Innovus/ICC2)

Job Responsibility

Serve as the middle-engineering technical leader at the intersection of RTL, physical design, and mixed-signal integration for Azure’s custom silicon programs
Ensure that design intent—digital and mixed-signal—is captured accurately in constraints, flows, and sign-off methodologies
Lead the capture and validation of design intent for digital and mixed-signal blocks, ensuring accurate constraints and seamless integration across front-end and physical design flows
Provide static timing leadership for mixed-signal interfaces, driving timing closure, exception quality, and correlation across corners
Partner closely with RTL, PD, mixed-signal, DFT, and CAD teams to resolve cross-domain issues and maintain alignment on timing, power, and functional requirements
Run, review and debug physical design flows, timing reports, ensuring consistency with synthesis and STA assumptions and driving convergence through targeted mitigations
Contribute to design automation including leveraging AI, constraint-checking, and flow improvements that enhance execution efficiency and PPA
Operate with limited direction, demonstrating strong ownership, attention to detail, and the ability to communicate clear, data-driven status, risks, and mitigation plans to program leadership

Fulltime

Principal Physical Design Manager

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

India , Bangalore

Salary:

Not provided

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Bachelor's or master’s in electrical or computer engineering or related field with 15+ years of experience
Experience in physical design implementation, signoff at block / sub system / sub-chip / SoC level
Experience in tapeouts of complex ASICs in leading edge technology
Ability to meet Microsoft, customer and/or government security screening requirements
This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
This role will require access to information that is controlled for export under export control regulations
As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status
To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport

Job Responsibility

Lead a team in defining implementation and execution plan for a schip/SOC
Execute the plan for successful tapeout by working with various stakeholders (RTL, IP, Methodology, DFT, Architecture etc)
Drive the to achieve the best performance, power, and area (PPA) for AI system-on-chips (SOCs)
Optimizing technology, libraries, physical design, RTL design, and architecture
Leading the team in defining the implementation and execution plan for a subchip/SOC
Collaborating with various stakeholders such as RTL designers, IP teams, Methodology experts, DFT engineers, and Architects to ensure a cohesive plan
Executing the defined plan to ensure successful tapeout of the subchip/SOC
Driving the team to achieve the best performance, power, and area (PPA) for AI system-on-chips
Optimizing technology choices, libraries, physical design methodologies, RTL design strategies, and architectural decisions to meet performance targets
Ensuring that the physical design aspects align with the overall project goals and timelines

Fulltime

Principal Physical Design Manager

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Raleigh

Salary:

139900.00 - 274800.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
Ability to meet Microsoft, customer and/or government security screening requirements
Ability to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
Ability to provide proof of country of citizenship or proof of US residency or other protected status for export control assessment
Bachelor's or master’s in electrical or computer engineering or related field with 10+ years of experience
Experience in physical design implementation, signoff at block / sub system / sub-chip / SoC level
Experience in tapeout of complex ASICs in leading edge process node technology
8+ years of hands-on experience in EDA vendor tools such as Fusion Compiler, VCLP, Primetime, Formality, or Cadence Innovus and Conformal

Job Responsibility

Lead a team in defining implementation and execution plan for a schip/SOC
Execute the plan for successful tapeout by working with various stakeholders (RTL, IP, Methodology, DFT, Architecture etc)
Drive the team to achieve the best performance, power, and area (PPA) for AI system-on-chips (SOCs)
Optimizing technology, libraries, physical design, RTL design, and architecture
Collaborate with various stakeholders such as RTL designers, IP teams, Methodology experts, DFT engineers, and Architects
Provide technical guidance and mentorship to team members
Oversee the development and implementation of physical design flows and methodologies
Collaborate with cross-functional teams to address design challenges and optimize for manufacturability
Monitor progress, identify risks, and implement mitigation strategies
Keep abreast of the latest industry trends, tools, and techniques in physical design

Fulltime

Physical Design Engineer

This individual contributor role sits within our physical design team and is cen...

Location

United States , San Francisco

Salary:

266000.00 - 445000.00 USD / Year

OpenAI

Expiration Date

Until further notice

Requirements

BS w/ 4+ or MS with 2+ or PhD with 0-1 year(s) of relevant industry experience in physical design and methodology development
Demonstrated success in taping out complex silicon designs
Hands-on experience with block physical implementation and PPA convergence
Strong coding experience with python, bazel, TCL
Strong experience building physical design tools, flows and methodologies
Strong understanding of microarchitecture, RTL design, physical design, circuit design, physical verification and timing closure
Deep familiarity with industry-standard tools and flows for physical synthesis, PNR, LEC and power estimation

Job Responsibility

Develop, build and own tools, flows and methodologies for physical implementation
Own physical implementation of floorplan blocks from floorplanning to final signoff
Collaborate with RTL designers to drive optimal block implementation solutions
Analyze and optimize design for timing, power, and area trade-offs, working in collaboration with EDA vendors and ASIC partners

What we offer

Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts
Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)
401(k) retirement plan with employer match
Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)
Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees
13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)
Mental health and wellness support
Employer-paid basic life and disability coverage
Annual learning and development stipend to fuel your professional growth
Daily meals in our offices, and meal delivery credits as eligible

Fulltime

Principal Logic Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Raleigh

Salary:

139900.00 - 274800.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements
This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
This role will require access to information that is controlled for export under export control regulations
As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status
To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport

Job Responsibility

Establish yourself as an integral member of a digital logic design team for the development of AI components with focus on micro-architectural based functions and features
Be responsible for the logic design/Register Transfer Level (RTL) entry, design quality including Lint, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), power etc., and timing closure of high-performance digital IP
Collaborate with the verification team to ensure the implementation meets both architectural and micro-architectural intent
Interface with physical design (PD), design for test (DFT), and other teams to optimize tradeoffs within the design
Provide technical leadership through mentorship and strong teamwork

Fulltime

Design Verification Engineer

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. ...

Location

United States , Sunnyvale

Salary:

120000.00 - 240000.00 USD / Year

Cerebras Systems

Expiration Date

Until further notice

Requirements

Advanced debugging and problem-solving skills
Deep knowledge of SystemVerilog testbench, DPI, and UVM
Excellent programming skills and knowledge of software engineering practices, including object-oriented design
Experience developing scalable and portable testbenches and components
Experience with verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection, and gate-level simulations
Proficient in scripting languages such as Python or Perl
Good interpersonal skills and the ability to work as a standout colleague are a must
Extremely self-motivated and eager to solve problems
3+ years of Design Verification experience

Job Responsibility

Work with architects, designers, post-silicon, and software engineers, to ensure a high-quality design that works for silicon
Develop and implement verification strategies, detailed tests, and coverage plans based on micro-architecture
Create verification methodologies and reusable environments, including components such as stimulus, checkers, assertions, and coverage
Implement tests, manage regressions, gather coverage, and debug test failures
Collaborate with cross-functional teams, including architecture, RTL design, physical design, firmware, and validation
Analyze and debug complex issues across simulation, emulation, and silicon bring-up phases
Continuously enhances verification infrastructure and flows to improve efficiency and quality
Contribute to the evolution of the overall verification methodology and best practices across the organization

What we offer

Build a breakthrough AI platform beyond the constraints of the GPU
Publish and open source their cutting-edge AI research
Work on one of the fastest AI supercomputers in the world
Enjoy job stability with startup vitality
Our simple, non-corporate work culture that respects individual beliefs

Fulltime

Head of Physical Design

We’re looking for a Head of Physical Design to lead the end-to-end RTL-to-GDSII ...

Location

United States , San Jose

Salary:

200000.00 - 300000.00 USD / Year

Etched

Expiration Date

Until further notice

Requirements

10+ years of experience in physical design for advanced-node ASICs, including multiple successful tapeouts
Demonstrated ownership of complex block- and full-chip physical implementation projects, from RTL handoff to signoff
Deep expertise in timing closure, including STA, path analysis, constraint management, and ECO optimization
Experience managing and mentoring physical design teams, ideally in fast-paced or startup environments
Strong scripting and automation skills (Python, Tcl) to optimize workflows and improve engineering velocity
Familiarity with leading EDA tools like Cadence Innovus, Synopsys ICC2, and Mentor Calibre
Comfort working in a high-performance, in-person engineering culture that values ambition and execution

Job Responsibility

Own and optimize all facets of physical design, including floorplanning, placement, CTS, routing, and timing closure for complex AI accelerators
Build and lead a high-performing PD team, including engineers focused on implementation, flows, and signoff
Define and drive physical signoff strategy, ensuring DRC, LVS, ERC, and CDC are achieved with margin
Partner closely with RTL, DV, backend, and methodologies teams to ensure seamless integration and handoff across the stack
Guide block-level and chip-level floorplanning with input on timing budgets, power domains, and interconnect strategy
Drive early architecture and microarchitecture input to reduce rework and enable schedule predictability
Interface with EDA vendors and the foundry to integrate cutting-edge tools, flows, and node-specific optimizations
Lead the development of automation scripts (e.g., Python, Tcl) to accelerate design cycles and increase flow robustness
Create telemetry and dashboards to track design health and ensure accurate KPIs across closure milestones
Deliver fast, production-grade silicon through aggressive, high-confidence planning and execution

What we offer

Medical, dental, and vision packages with generous premium coverage
$500 per month credit for waiving medical benefits
Housing subsidy of $2k per month for those living within walking distance of the office
Relocation support for those moving to San Jose (Santana Row)
Various wellness benefits covering fitness, mental health, and more
Daily lunch + dinner in our office

Fulltime

Senior Engineer - Design for Test (DFT)

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Hillsboro

Salary:

119800.00 - 234700.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience
equivalent experience
4+ years of experience in the field of DFT knowledge about industry standard practice in Design for Test
ATPG, JTAG, Memory BIST, and trade-offs between test quality and test time
Ability to meet Microsoft, customer and/or government security screening requirements
Microsoft Cloud Background Check

Job Responsibility

Own block level DFT u-arch specification documentation & provide Test solutions in design for test chips and products
Ensure DFX goals (testability, debug, manufacturability, System Test, System Debug, Repair) are met by these IPs, ensure analog to digital boundaries are reliably tested. Review coverage metrics for Digital logic
Maintain & enhance existing DFT tools by understanding product needs & tailor solutions for current and upcoming products, also with the use of AI
Provide test plans and engage closely with verification engineers to perform waveform reviews
Ensure RTL quality pre-DFT to ensure the RTL is good for DFT insertion and coverage
Hold a primary role in enabling silicon by working directly with test engineers to bring up test vectors, and analyzing yield & diagnosis
Work as part of DFX (Test & Debug) team & closely collaborate with highly energetic cross functional team members (Architects, front-end & back-end design/verification, Physical design, and post-silicon manufacturing) with respect and with One Microsoft mentality to establish synergies

Fulltime

AI Silicon Physical Design Engineer

Cerebras Systems

Location:
United States , Sunnyvale

Category:
IT - Software Development

Contract Type:
Not provided

Salary:

Job Description:

Job Responsibility:

Requirements:

Nice to have:

Additional Information:

Job Posted:
February 17, 2026

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AI Silicon Physical Design Engineer

Cerebras Systems

Location:United States , Sunnyvale

Category:IT - Software Development

Contract Type:Not provided

Salary:

Job Description:

Job Responsibility:

Requirements:

Nice to have:

Additional Information:

Job Posted:February 17, 2026

Looking for more opportunities? Search for other job offers that match your skills and interests.

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Job Posted:
February 17, 2026