Ai/ml Silicon Design Engineer Job at AMD (Iasi)

Software System Designer 2

This is an exciting role in which you will have excellent exposure to all the la...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Strong object-oriented design concepts
Experience in at least one of the following - .Net, C#, C++, Database (Ex MSSQL)
Good knowledge of Programming concepts, Data Structures
Work/Academic experience in AI/ML development will be a plus
Knowledge/Experience in Semi-conductor domain will be a plus
Work experience of 2+ years
Bachelors or master’s degree in electrical engineering, Computer Science, Engineering, or an equivalent

Job Responsibility

Software application Design, Development
Drive innovation
Evaluate and review of existing processes and continuously strive to optimize the workflow
Develop, Test, and Support of debug tools that will be used by the Silicon Engineering teams and Customers
Collaborating with peers, technical leads on tooling support & solutions
Develop /Maintain/support software features
Participate in design reviews, and quality improvements
Engage as a teammate, and always ready to seek new challenges

New

Post-Silicon Validation Engineer

We are seeking a highly skilled and motivated Post Silicon Validation Engineer t...

Location

United States , San Jose

Salary:

160000.00 - 260000.00 USD / Year

Etched

Expiration Date

Until further notice

Requirements

7+ years of experience in post-silicon validation, bring-up, and debug of ASICs (preferably including AI/ML accelerators)
Proven expertise in early silicon bring-up, debug, and validation
Deep knowledge of peripheral interfaces and board-level debug
Proficiency in C, Python, and scripting for validation automation
Hands-on expertise with oscilloscopes, logic/protocol analyzers, and other validation lab tools
Familiarity with firmware, bootloaders, and low-level silicon debug environments
Strong problem-solving, analytical, and collaboration skills across hardware and software teams
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's preferred)

Job Responsibility

Drive early bring-up of first silicon, including boot, initialization, and debug of ASICs
Perform deep-dive debug of silicon issues across RTL, firmware, and system levels
Collaborate closely with design, verification, and board teams to root-cause and resolve functional and electrical issues
Validate and characterize custom IP blocks and accelerator components
Execute functional and performance validation of compute units and specialized processing elements
Conduct IP-level and full-chip stress testing and corner case analysis to ensure robust operation
Develop and extend post-silicon validation infrastructure, automation, and test suites
Implement efficient result capture, analysis, and regression frameworks
Utilize lab instrumentation (oscilloscopes, analyzers, BERTs, pattern generators) for detailed signal and system characterization
Define validation strategies and coverage metrics across design blocks and subsystems

What we offer

Medical, dental, and vision packages with generous premium coverage
$500 per month credit for waiving medical benefits
Housing subsidy of $2k per month for those living within walking distance of the office
Relocation support for those moving to San Jose (Santana Row)
Various wellness benefits covering fitness, mental health, and more
Daily lunch + dinner in our office
Plus Significant Equity

Fulltime

New

RTL & Co-design Engineer

OpenAI’s Hardware organization develops silicon and system-level solutions desig...

Location

United States , San Francisco

Salary:

225000.00 - 445000.00 USD / Year

OpenAI

Expiration Date

Until further notice

Requirements

Graduate-level research or industry experience in computer architecture, AI/ML hardware–software co-design, including workload analysis, dataflow mapping, or accelerator algorithm optimization
Expertise writing production-quality RTL in Verilog/SystemVerilog, with a track record of delivering complex blocks to tape-out
Experience developing hardware design models or architectural simulators, ideally for AI/ML or high-performance compute systems
Familiarity with industry-standard design tools (lint, CDC/RDC, synthesis, STA) and methodologies
Ability to work cross-functionally with architecture, ML systems, compilers, and verification teams
Strong problem-solving skills and ability to think across abstraction layers, from algorithms to circuits
Passion for building industry-leading massive-scale hardware systems
To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations.

Job Responsibility

Produce clean, production-quality microarchitecture and RTL for major accelerator subsystems
Contribute to architectural studies including performance modeling and feasibility analysis
Collaborate with software, simulator, and compiler teams to ensure hardware/software co-design and workload fit
Partner with DV and PD to ensure functional correctness, timing closure, area/power targets, and clean integration
Build and review performance and functional models to validate design intent
Participate in design reviews, documentation, and bring-up support across the full silicon lifecycle.

What we offer

Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts
Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)
401(k) retirement plan with employer match
Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)
Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees
13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)
Mental health and wellness support
Employer-paid basic life and disability coverage
Annual learning and development stipend to fuel your professional growth
Daily meals in our offices, and meal delivery credits as eligible

Fulltime

New

Senior VLSI Product and Test Engineer

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. ...

Location

United States , Sunnyvale

Salary:

175000.00 - 275000.00 USD / Year

Cerebras Systems

Expiration Date

Until further notice

Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
10+ years of hands-on experience in semiconductor test engineering with a focus on large-scale integration
Proven track record in wafer-scale testing, AI/ML accelerator testing, or large parallel processor/GPUs with SRAM, DDR-DRAM, HBM
Expert-level Advantest 93K experience with Teradyne as an alternative
Experienced in advanced interconnect testing (mesh networks, NoC, high-speed serial links)
Expertise in High-Speed Serdes testing at ATE, package, and system level
Experience in handling analog blocks in large digital ASICs
Expertise in load-board and probe-card specification, design, development, and debug for advanced DFT implementation that comprises boundary scan, scan, BIST, ATPG, and functional tests
Test program development and optimization
Production test debugging, and yield improvement

Job Responsibility

Design and develop comprehensive test programs for wafer-scale processors and large-scale AI/ML accelerator chips
Implement sophisticated DFT strategies for wafer-scale designs, including hierarchical scan chains and distributed BIST
Create scalable test methodologies for testing hundreds to thousands of processing cores on a single wafer, with distributed SRAM
Develop fault isolation techniques for identifying defective cores/tiles within wafer-scale processors
Implement efficient wafer-level test flows that can handle massive parallelism and complex interconnect structures such as mesh networks, on-chip NoC, and die-to-die communication
Work with the DFT engineers, silicon architects/designers, performance engineers, and software engineers to enhance the testability of Wafer Scale Engines
Work refining test programs for di/dt, V-F characterization space, current and temperature limits
Optimize test programs for testing multiple die simultaneously while maintaining test quality
Develop innovative approaches for power delivery and thermal management during wafer-level testing
Develop test strategies for wafer-scale integration-testing, yield optimization, redundancy, and fault tolerance verification

What we offer

Bonus and equity
Build a breakthrough AI platform beyond the constraints of the GPU
Publish and open source their cutting-edge AI research
Work on one of the fastest AI supercomputers in the world
Enjoy job stability with startup vitality
Simple, non-corporate work culture that respects individual beliefs

Fulltime

New

RTL & Codesign Engineer

OpenAI’s Hardware organization develops silicon and system-level solutions desig...

Location

United States , San Francisco

Salary:

225000.00 - 445000.00 USD / Year

OpenAI

Expiration Date

Until further notice

Requirements

Graduate-level research or industry experience in computer architecture, AI/ML hardware–software co-design, including workload analysis, dataflow mapping, or accelerator algorithm optimization
Expertise writing production-quality RTL in Verilog/SystemVerilog, with a track record of delivering complex blocks to tape-out
Experience developing hardware design models or architectural simulators, ideally for AI/ML or high-performance compute systems
Familiarity with industry-standard design tools (lint, CDC/RDC, synthesis, STA) and methodologies
Ability to work cross-functionally with architecture, ML systems, compilers, and verification teams
Strong problem-solving skills and ability to think across abstraction layers, from algorithms to circuits
Passion for building industry-leading massive-scale hardware systems
To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations.

Job Responsibility

Produce clean, production-quality microarchitecture and RTL for major accelerator subsystems
Contribute to architectural studies including performance modeling and feasibility analysis
Collaborate with software, simulator, and compiler teams to ensure hardware/software co-design and workload fit
Partner with DV and PD to ensure functional correctness, timing closure, area/power targets, and clean integration
Build and review performance and functional models to validate design intent
Participate in design reviews, documentation, and bring-up support across the full silicon lifecycle

What we offer

Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts
Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)
401(k) retirement plan with employer match
Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)
Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees
13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)
Mental health and wellness support
Employer-paid basic life and disability coverage
Annual learning and development stipend to fuel your professional growth
Daily meals in our offices, and meal delivery credits as eligible

Fulltime

New

ASIC Architect

We are seeking a talented Computer Architect to join our architecture team and c...

Location

United States , San Jose

Salary:

200000.00 - 265000.00 USD / Year

Etched

Expiration Date

Until further notice

Requirements

PhD in Computer Science, Electrical Engineering, Computer Engineering, or related field
5+ years of experience in computer architecture, ASIC design, or related fields
Strong understanding of computer architecture fundamentals including pipelines, memory hierarchies, and interconnects
Experience with performance modeling and architectural simulation tools
Hands‑on experience designing and optimizing floating‑point datapaths or arithmetic‑intensive circuits and working with advanced process nodes
Proficiency in Rust, C/C++, or Python for modeling and analysis
Knowledge of modern processor microarchitecture and design tradeoffs
Strong analytical and problem-solving skills with attention to detail
Excellent communication skills and ability to work in cross-functional teams

Job Responsibility

Microarchitecture & dataflow innovation: Design and analyze chip architectures optimized for AI/ML workloads, with focus on throughput, latency, and power efficiency
Design next-generation silicon: Contribute to power and area estimation methodologies for early-stage, next generation architectural exploration
Custom circuit development: Create architectural specifications and interface definitions for compute blocks and subsystems
System‑level prototyping: Collaborate with RTL, verification, physical design, and software teams to ensure architectural feasibility and ultimate optimization
Performance optimization: Conduct architectural experiments using cycle-accurate simulators and analytical models
Cross‑functional collaboration: Support integration efforts by providing architectural guidance and resolving design challenges

What we offer

Medical, dental, and vision packages with generous premium coverage
$500 per month credit for waiving medical benefits
Housing subsidy of $2k per month for those living within walking distance of the office
Relocation support for those moving to San Jose (Santana Row)
Various wellness benefits covering fitness, mental health, and more
Daily lunch + dinner in our office

Fulltime

Director, Digital Ecosystem Applications

This position is responsible for the Software Platforms group at the Innovation ...

Location

United States , Belmont

Salary:

240000.00 - 285000.00 USD / Year

Volkswagen AG

Expiration Date

Until further notice

Requirements

10+ years with 2+ years in a technical leadership role
CS, EE, M.S. Engineering (or equivalent) REQUIRED
M.S. Engineering (or equivalent) or PhD PREFERRED
Analytical and conceptual thinking – using logic and reason, creative and strategic
Communication skills – interpersonal, presentation and written
Managing interdisciplinary teams on individual projects
Integration – joining people, processes or systems
Influencing and negotiation skills
Problem solving
Resource management

Job Responsibility

Define the technical mission, architecture strategy, and long‑term platform vision for the In‑Vehicle Computing & Digital Ecosystem Applications team, spanning Android Automotive OS (AAOS), in‑vehicle compute platforms, Software‑Defined Vehicle (SDV) architecture, and AI‑driven cockpit intelligence
Provide technical leadership across the full software stack, including Android Framework, System Services, HAL layers, middleware, connectivity stacks, media/audio frameworks, HMI toolchains, and cloud‑connected AI runtimes within an SDV‑aligned architecture
Lead and mentor engineering teams in platform bring‑up, system integration, performance optimization, and development of AI‑agentic features, multimodal interaction models, and next‑generation speech technologies
Manage multi‑year budgets for platform development, AI integration, SDV‑aligned compute evolution, SoC evaluations, cloud services, and prototype programs
Deliver executive‑level technical reporting on architecture decisions, platform readiness, SDV integration milestones, AI progress, risks, and strategic recommendations
Drive strategic planning for ICC’s infotainment and cockpit portfolio, including AAOS evolution, hybrid cloud/edge AI pipelines, intelligent mobile agent technologies, and SDV‑centric software and compute roadmaps
Align technical roadmaps with global VW Group Innovation teams across infotainment, connectivity, AI/ML, vehicle architecture, cloud services, and SDV platform strategy, ensuring cross‑platform consistency and shared component reuse
Build strategic relationships with SoC vendors, Tier‑1 suppliers, cloud providers, and AI technology partners to influence cockpit compute and SDV platform evolution
Maintain partnerships with Silicon Valley companies specializing in AI runtimes, LLMs, speech, multimodal interaction, and automotive‑grade SDV‑compatible software frameworks
Collaborate with academic and research institutions on AI‑agentic systems, embedded ML, HMI, and in‑vehicle compute architectures aligned with SDV principles

What we offer

Eligibility for annual performance bonus
Healthcare benefits
401(k), with company match
Defined contribution retirement program
Tuition reimbursement
Company lease car program
Paid time off

Fulltime

New

Software Engineering Technical Leader

Lead the design and development of software features for Cisco’s Silicon One NPU...

Location

United States of America , San Jose

Salary:

210600.00 - 350800.00 USD / Year

Duo Security

Expiration Date

April 13, 2026

Requirements

Bachelors + 12 years of related experience, or Masters + 8 years of related experience, or PhD + 5 years of related experience in an Engineering role
Experience using C++ and Python for programming and design
Experience in algorithms and data structures
Experience with Layer 2 and Layer 3 networking protocols and technologies, traffic management and congestion management

Job Responsibility

Lead the design and development of software features for Cisco’s Silicon One NPU
Create software to build highly scalable, low power, low latency, dense systems for AI/ML workloads, internet users and applications
Use modern C++, Network processing language of Silicon One and Python to develop software on the NPU
Participate in requirement discussions with the customer and work on scoping the feature post-closing the requirements
Take complete ownership of delivering the software in a timely manner and with outstanding quality
Lead a team of engineers and guide/unblock the team with any design/implementation related issues
Be the gatekeeper of the code base in the domains you own
Gain intimate knowledge of the Silicon One hardware architecture, software programming models and work with the architecture and hardware teams to define the next generation of ASIC products

What we offer

Medical, dental and vision insurance
401(k) plan with a Cisco matching contribution
Paid parental leave
Short and long-term disability coverage
Basic life insurance
10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
Paid year-end holiday shutdown
4 paid days off for personal wellness
Non-exempt employees receive 16 days of paid vacation time per full calendar year

Fulltime

Ai/ml Silicon Design Engineer

AMD

Location:
Romania , Iasi

Category:
IT - Software Development

Contract Type:
Not provided

Salary:

Job Description:

Job Responsibility:

Requirements:

Additional Information:

Job Posted:
January 06, 2026

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