Principal Design Engineer United States Jobs (Hybrid work)

Taara (Google's Moonshot Factory) seeks a Principal Analog/Mixed-Signal ASIC Design Engineer in Sunnyvale to develop next-gen photonic modules. Requires PhD, 10+ years experience, and BCD tapeout expertise.

Lead GPU server and rack-scale infrastructure design for a fast-growing AI cloud platform in Bellevue, WA. Hybrid Principal role driving NVIDIA/AMD architecture, ODM partnerships, and next-gen AI compute at production scale.

Principal Analog Design Engineer in Duluth to architect and verify CMOS analog blocks for custom ASICs. Requires 10-15 years of analog design experience and DDR5/DDR6 I/O expertise.

Renesas seeks a Principal Digital Design Engineer in San Jose to lead SOC architecture and RTL development. Requires 8+ years experience, strong protocol knowledge, and offers a dynamic, multicultural environment.

Renesas seeks a Principal Digital Design Engineer in San Jose to lead SOC architecture and RTL design. Requires MSEE/PhD with 8+ years experience, strong protocol knowledge, and AI-savvy mindset.

Renesas seeks a Principal Digital Design Engineer in San Jose to lead SOC architecture and RTL design. Requires 8+ years experience, strong protocol knowledge, and offers a dynamic, multicultural environment.

Lead digital design for advanced power management ICs in Austin. Requires 10+ years EE/ECE experience, Verilog expertise, and strong debug skills. Mentor junior engineers and drive innovative chip development.

Lead verification strategy for next-gen DDR6 semiconductor memory interfaces in Plano. Requires deep SystemVerilog and UVM expertise, technical ownership of complex verification efforts, and strong collaboration with RTL design teams.

Lead verification strategy for next-gen DDR6 semiconductor memory interfaces in Austin. Requires deep SystemVerilog and UVM expertise, technical ownership of complex verification efforts, and collaboration with RTL teams. DDR experience a plus.

Lead verification strategy for next-gen DDR6 semiconductor memory interfaces in Duluth. Requires deep SystemVerilog and UVM expertise, technical ownership of complex verification efforts, and collaboration with RTL design teams. DDR experience a plus.

Lead verification strategy for next-gen DDR6 semiconductor memory interfaces in Chandler. Requires deep SystemVerilog and UVM expertise, technical ownership of complex verification efforts, and strong collaboration with RTL design teams.

Lead verification strategy for next-gen DDR6 memory interface products in San Jose. Requires deep SystemVerilog and UVM expertise, technical ownership of complex semiconductor verification, and close collaboration with RTL teams.

Lead advanced semiconductor packaging development at Renesas in San Jose. Requires MSc/PhD, 5+ years packaging experience, and expertise in WLP, 2.5D/3D, SiP, and flip-chip technologies.

Lead the architectural evolution of PMIC and mixed-signal products as a global technical authority in Chandler. Requires 12+ years in power management, CMOS expertise, and proven technical leadership on complex ICs.

Lead digital design projects for advanced power management ICs in Austin. Requires 10+ years EE/ECE experience, Verilog expertise, and strong leadership skills. Mentor junior engineers and drive innovation.