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Design Verification Engineer United States Jobs

30 Job Offers

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Principal Design Verification Engineer (AI Fabric Switches)
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Hardware Engineer II - Design Verification
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Join HPR as a Hardware Engineer II in Needham, MA, verifying high-performance FPGA systems for electronic trading. Requires 2+ years of verification experience, SystemVerilog skills, and a BS/MS in a related field.
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Senior or Staff Design Verification Engineer
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Powerlattice seeks a Senior/Staff Design Verification Engineer in Vancouver, US, to lead SoC/IP verification with SystemVerilog, UVM, and formal methods. Requires 10+ years experience. Offers stock options and full benefits.
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DRAM Principal Design Verification Engineer
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Lead DRAM design verification at Micron in Boise. Drive UVM-based testbenches, AI-powered automation, and coverage closure for next-gen memory. Requires 10+ years, SystemVerilog/UVM expertise, and strong technical leadership.
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Senior Design Verification Engineer
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Join Micron as a Senior Design Verification Engineer in San Jose, CA. Develop CAD tools, automation, and flows for advanced memory design. Requires 5+ years EDA/CAD experience, Python, and VLSI fundamentals.
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Principal Design Verification Engineer- SerDes/PHY IP
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Lead SerDes/PHY IP verification at Astera Labs in San Jose. Requires 8+ years in UVM/SystemVerilog, mixed-signal co-simulation, and high-speed protocols like PCIe or CXL. Architect verification for AI connectivity solutions.
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Senior Scientist I, Engineering - Design Verification Engineer
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AbbVie seeks a Senior Scientist I, Design Verification Engineer in North Chicago to lead lab verification for drug-device combination products. Requires 10+ years experience, ISO/FDA knowledge, and GMP expertise.
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Principal Design Verification Engineer
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Lead verification strategy for next-gen DDR6 semiconductor memory interfaces in Plano. Requires deep SystemVerilog and UVM expertise, technical ownership of complex verification efforts, and strong collaboration with RTL design teams.
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Principal Design Verification Engineer
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Lead verification strategy for next-gen DDR6 semiconductor memory interfaces in Austin. Requires deep SystemVerilog and UVM expertise, technical ownership of complex verification efforts, and collaboration with RTL teams. DDR experience a plus.
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Principal Design Verification Engineer
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Lead verification strategy for next-gen DDR6 semiconductor memory interfaces in Duluth. Requires deep SystemVerilog and UVM expertise, technical ownership of complex verification efforts, and collaboration with RTL design teams. DDR experience a plus.
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Principal Design Verification Engineer
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Lead verification strategy for next-gen DDR6 semiconductor memory interfaces in Chandler. Requires deep SystemVerilog and UVM expertise, technical ownership of complex verification efforts, and strong collaboration with RTL design teams.
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Principal Design Verification Engineer
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Lead verification strategy for next-gen DDR6 memory interface products in San Jose. Requires deep SystemVerilog and UVM expertise, technical ownership of complex semiconductor verification, and close collaboration with RTL teams.
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Staff Design Verification Engineer
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Renesas seeks a Staff Design Verification Engineer in Duluth to verify advanced DDR6 memory interface products for data center and AI. Requires 8+ years in semiconductor verification, strong SystemVerilog and UVM skills.
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Senior Staff Design Verification Engineer
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Renesas seeks a Senior Staff Design Verification Engineer in Duluth to lead verification of advanced memory interface products for data center and AI. Requires 10+ years in semiconductor verification, SystemVerilog and UVM expertise.
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Senior Digital Design Verification Engineer
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Senior Principal Design Verification Engineer
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Design Verification Engineer (Lab Project Specialist)
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Design Verification Engineer - SoC
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Design Verification Engineer - Interface IP
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Design Verification Engineer - Internal IP
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About the Design Verification Engineer role

Design Verification Engineer jobs represent a critical pillar in the semiconductor and hardware development industry, ensuring that complex integrated circuits and systems-on-chip (SoCs) function correctly before they are manufactured. Professionals in this role act as the quality gatekeepers of the digital design world, tasked with the rigorous process of confirming that a design meets its specified requirements and operates without critical bugs. The primary responsibility of a Design Verification Engineer is to create and execute comprehensive verification plans. This involves developing sophisticated testbenches using industry-standard methodologies like Universal Verification Methodology (UVM) and languages such as SystemVerilog, Verilog, and C++.

They write both directed and constrained-random tests to stress-test the design, simulating millions of possible scenarios to uncover hidden flaws. A significant part of the daily work involves debugging test failures, working closely with RTL designers to identify whether a bug lies in the design itself or in the test environment. They use advanced simulation tools to analyze waveforms and trace logic errors, ensuring that every functional corner case is covered. Coverage analysis is another core duty; engineers must track code coverage and functional coverage metrics to guarantee that no part of the design remains untested.

This often requires modifying tests or adding new ones to meet strict coverage goals. Beyond pre-silicon simulation, many Design Verification Engineer jobs involve post-silicon validation, where they help bring up actual silicon in the lab, running tests on real hardware to ensure it matches simulation results. They also work with emulation platforms to run software workloads at higher speeds, bridging the gap between simulation and final production. Collaboration is essential, as these engineers interface daily with architects, design engineers, firmware teams, and design-for-test (DFT) specialists to align verification strategies and resolve issues early in the development cycle.

Typical skills required for these roles include deep proficiency in SystemVerilog and UVM, strong debugging abilities, and experience with scripting languages like Perl, Python, or Makefile for automation. A solid understanding of digital logic design, computer architecture, and protocols is also crucial. Most positions require a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field, coupled with several years of hands-on verification experience. As chips grow more complex—integrating AI accelerators, advanced graphics, and high-speed interfaces—the demand for meticulous and innovative Design Verification Engineer jobs continues to rise, making this profession indispensable for delivering reliable, high-performance silicon to market.