ASIC Design Verification Engineer Jobs

Senior ASIC Design Verification Engineer sought by Cisco’s Common Hardware Group in Bangalore. Leverage 7+ years of UVM/System Verilog expertise to architect and build top-level DV environments for cutting-edge Cisco Silicon One ASICs. Drive verification from test bench creation to post-silicon b...

Join our ASIC team in Santa Clara as a Design Verification Engineer. You will verify next-generation firewall ASICs using SystemVerilog, UVM, and advanced methodologies. This role involves creating test plans, developing testbenches, and ensuring coverage from simulation to silicon validation. Br...

Lead pre-silicon verification for next-gen firewall ASICs in Santa Clara. Define methodologies, architect test benches, and ensure coverage using SystemVerilog/UVM. Requires 5+ years' experience taking ASICs from concept to production. Expertise in simulation, emulation, and formal verification i...

Join Meta's cutting-edge hardware team as an ASIC Design Verification Engineer in Austin. You will verify complex IP/SoC designs using SystemVerilog/UVM and Python/TCL scripting. This role requires a Bachelor's degree and 1+ year of experience in UVM-based verification. We offer a competitive pac...

Join Meta's cutting-edge hardware team as an ASIC Design Verification Engineer in Sunnyvale. You will develop verification plans, build testbenches using SystemVerilog/UVM, and ensure design quality for next-gen technologies. This role requires a Master's and 2+ years of experience in ASIC verifi...

Join Meta as an ASIC Design Verification Engineer in Sunnyvale. You will verify cutting-edge IP and SoCs for data centers using SystemVerilog/UVM, formal methods, and emulation. This role requires a relevant degree and 2+ years of hands-on verification experience. We offer a competitive package i...

Join Meta's Infrastructure team in Bangalore as an ASIC Engineer Intern, specializing in Design Verification. You will verify advanced IPs using SystemVerilog/UVM, contributing to "Green" data center accelerators. This 12-16 week internship requires a background in Electrical/Computer Engineering...

Join Meta's Infrastructure team as an ASIC Design Verification Engineer in Sunnyvale. You will verify IP and SoC designs for data centers using SystemVerilog/UVM, formal methods, and emulation. This role requires 6+ years of experience and offers collaboration with industry experts, plus bonus an...