ASIC Design Verification Engineer Jobs

Senior ASIC Digital Design Engineer role in Hsinchu, Taiwan, verifying configurable system-level IP and subsystems for next-gen RISC-V platforms. Requires a Master's degree and hands-on Verilog/SystemVerilog, C/C++ or Python skills.

Meta seeks a Staff ASIC Design Verification Engineer in Sunnyvale, CA to lead UVM-based verification for custom silicon powering AI/ML, networking, and video processing. You will architect scalable environments, drive end-to-end IP/SoC verification, and collaborate with design teams to ensure fir...

Join a top-tier ASIC team in Santa Clara as a Sr Design Verification Engineer, driving next-gen firewall ASICs from concept to mass production. Leverage SystemVerilog and UVM to architect test benches, define coverage, and debug across simulation, emulation, and formal verification. Ideal candida...