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Asic Design Engineer United States, Roseville Jobs

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ASIC Design Engineer
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Join HPE Aruba Networking in Roseville as an ASIC Design Engineer. Contribute to next-gen networking silicon architecture using VLSI principles and Verilog/SystemVerilog. This role requires a degree in EE/CE, 0-4 years' experience, and offers benefits in health, development, and inclusion. Collab...
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United States , Roseville
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89400.00 - 206500.00 USD / Year
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Hewlett Packard Enterprise
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Until further notice
ASIC Design Engineer
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Join HPE Aruba Networking in Roseville as an ASIC Design Engineer. Lead VLSI projects from architecture to physical implementation using Verilog/SystemVerilog and EDA tools. This role requires 6-10 years of experience and offers a focus on innovation, mentorship, and comprehensive wellbeing benef...
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Location
United States , Roseville
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Salary
130500.00 - 300000.00 USD / Year
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Hewlett Packard Enterprise
Expiration Date
Until further notice
Explore a world of opportunity in ASIC Design Engineer jobs, a critical and highly specialized field at the heart of modern technology. ASIC (Application-Specific Integrated Circuit) Design Engineers are the master architects behind the custom silicon chips that power everything from smartphones and data centers to automotive systems and AI accelerators. Their work involves transforming abstract concepts and system requirements into tangible, high-performance, and power-efficient integrated circuits. A career in ASIC design is typically segmented into two primary, interconnected domains: front-end and back-end design. Front-end engineers focus on the logical creation of the chip. They work closely with system architects to define specifications, then use Hardware Description Languages (HDLs) like Verilog or SystemVerilog to code the chip's functionality at the Register Transfer Level (RTL). A significant part of their role involves rigorous simulation and verification to ensure the design is logically flawless before it moves to the physical implementation stage. They develop complex testbenches and use advanced methodologies like UVM to catch bugs early, which is crucial given the immense cost of respinning a physical chip. Back-end engineers, often called Physical Design Engineers, take the verified RTL and turn it into a physical blueprint ready for manufacturing. This intricate process involves synthesis, which converts the RTL into a gate-level netlist, followed by floorplanning, where the chip's layout is strategically mapped out. They then perform placement and clock tree synthesis (CTS) to optimize timing and power distribution, and routing, which connects all the millions of transistors. Throughout this process, they must continuously analyze and fix challenges related to timing, power integrity (EM/IR), and signal integrity to meet all performance and reliability goals, culminating in a final GDSII file sent for fabrication. Typical responsibilities across these roles include collaborating with cross-functional teams including verification, architecture, and packaging; performing timing analysis; implementing design changes (ECOs); and running physical verification checks (DRC, LVS) to ensure the design is manufacturable. Professionals in this field are expected to have a strong foundation in digital logic design, computer architecture, and semiconductor physics. Proficiency with industry-standard EDA tools from vendors like Synopsys and Cadence is essential, as is experience with scripting languages like TCL, Perl, or Python to automate workflows. A bachelor's or master's degree in Electrical or Computer Engineering is a standard requirement, with senior positions demanding extensive experience and a proven track record of successful tape-outs, especially in advanced process nodes like 7nm and below. The search for ASIC Design Engineer jobs leads to a rewarding career for those who are detail-oriented, adept at problem-solving, and passionate about building the foundational technology of tomorrow. If you have a blend of creative engineering and analytical rigor, this profession offers a challenging and impactful path in shaping the future of electronics.

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