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Asic Design Engineer United States Jobs

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ASIC Physical Design Engineer
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Join Cisco Acacia's silicon team as an ASIC Physical Design Engineer. Drive RTL-to-GDSII implementation for cutting-edge transceivers on advanced nodes (sub-7nm to 2nm). Utilize your expertise in place & route, STA, and tools like Innovus or ICC2. Enjoy a unique startup culture within a global le...
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United States of America , Maynard
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122000.00 - 172100.00 USD / Year
Cisco
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ASIC Design Engineer
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United States , Milpitas
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95981.00 - 135896.00 USD / Year
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Sandisk
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ASIC Engineer, Design
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Join Meta as an ASIC Design Engineer in Sunnyvale. Develop advanced low-power hardware accelerators and SoCs for ML, graphics, and networking. Requires 6+ years of production silicon design experience with RTL and microarchitecture. Enjoy a competitive package including bonus and equity.
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United States , Sunnyvale
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146000.00 - 209000.00 USD / Year
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Meta
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ASIC Engineer, Design Verification
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Join Meta as an ASIC Design Verification Engineer in Sunnyvale. You will verify cutting-edge IP and SoCs for data centers using SystemVerilog/UVM, formal methods, and emulation. This role requires a relevant degree and 2+ years of hands-on verification experience. We offer a competitive package i...
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United States , Sunnyvale
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114000.00 - 172000.00 USD / Year
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Meta
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ASIC Design Engineer II
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Join AWS to design custom SoCs powering our Machine Learning servers. As an ASIC Design Engineer II in Cupertino, you'll develop high-performance, power-efficient RTL using SystemVerilog. Collaborate on cutting-edge hardware like AWS Inferentia, optimizing for performance, power, and area. Enjoy ...
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United States , Cupertino
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165200.00 - 223600.00 USD / Year
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Amazon Pforzheim GmbH
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ASIC Design Engineer
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Join HPE Aruba Networking in Roseville as an ASIC Design Engineer. Contribute to next-gen networking silicon architecture using VLSI principles and Verilog/SystemVerilog. This role requires a degree in EE/CE, 0-4 years' experience, and offers benefits in health, development, and inclusion. Collab...
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United States , Roseville
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89400.00 - 206500.00 USD / Year
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Hewlett Packard Enterprise
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ASIC Design Engineer
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Join HPE Aruba Networking in Roseville as an ASIC Design Engineer. Lead VLSI projects from architecture to physical implementation using Verilog/SystemVerilog and EDA tools. This role requires 6-10 years of experience and offers a focus on innovation, mentorship, and comprehensive wellbeing benef...
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United States , Roseville
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130500.00 - 300000.00 USD / Year
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Hewlett Packard Enterprise
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Asic Physical Design Engineer
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Join our team in San Jose as an ASIC Physical Design Engineer. You will lead large SoC implementations from RTL to GDSII, focusing on floorplanning, power grid, and clock network design. We require 7+ years of experience in full-chip physical design and verification. We offer a comprehensive bene...
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United States , San Jose
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148000.00 - 340500.00 USD / Year
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Hewlett Packard Enterprise
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Asic digital design engineer
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Join Idaho Scientific as an ASIC Digital Design Engineer in Boise or Salt Lake City. This role requires US Citizenship and involves developing secure CPU and SoC architectures using SystemVerilog/VHDL. You'll refine microarchitecture, perform RTL design, and ensure timing closure. We offer compet...
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United States , Boise; Salt Lake City
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Not provided
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Idaho Scientific
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ASIC Digital Design Engineering Lead
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Lead a team designing secure ASICs for defense and critical infrastructure. This role requires US Citizenship, 5+ years of FPGA/ASIC experience, and proven leadership. You will define microarchitecture, implement RTL, and guide products from spec to production. Enjoy competitive benefits in Boise...
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United States , Boise; Salt Lake City
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Not provided
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Idaho Scientific
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Senior/Principal ASIC Digital Design Engineer
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Seeking a Senior/Principal ASIC Digital Design Engineer for secure CPU and SoC development. This role requires US Citizenship, 5+ years of ASIC/FPGA experience, and expertise in RTL design and verification. Enjoy competitive benefits while working on critical security solutions in Boise or Salt L...
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United States , Boise; Salt Lake City
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Not provided
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Idaho Scientific
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ASIC Engineer, Design Verification
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Join Meta's Infrastructure team as an ASIC Design Verification Engineer in Sunnyvale. You will verify IP and SoC designs for data centers using SystemVerilog/UVM, formal methods, and emulation. This role requires 6+ years of experience and offers collaboration with industry experts, plus bonus an...
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United States , Sunnyvale
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146000.00 - 209000.00 USD / Year
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Meta
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ASIC Engineer, Physical Design
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Join Meta's Infrastructure team as an ASIC Physical Design Engineer in Sunnyvale. You will own the physical implementation of high-performance, low-power SoCs from Netlist to GDSII in advanced nodes (5nm and below). This role requires expertise in large-scale designs (>20M gates, 1GHz+), EDA tool...
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United States , Sunnyvale
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146000.00 - 209000.00 USD / Year
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Meta
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Explore a world of opportunity in ASIC Design Engineer jobs, a critical and highly specialized field at the heart of modern technology. ASIC (Application-Specific Integrated Circuit) Design Engineers are the master architects behind the custom silicon chips that power everything from smartphones and data centers to automotive systems and AI accelerators. Their work involves transforming abstract concepts and system requirements into tangible, high-performance, and power-efficient integrated circuits. A career in ASIC design is typically segmented into two primary, interconnected domains: front-end and back-end design. Front-end engineers focus on the logical creation of the chip. They work closely with system architects to define specifications, then use Hardware Description Languages (HDLs) like Verilog or SystemVerilog to code the chip's functionality at the Register Transfer Level (RTL). A significant part of their role involves rigorous simulation and verification to ensure the design is logically flawless before it moves to the physical implementation stage. They develop complex testbenches and use advanced methodologies like UVM to catch bugs early, which is crucial given the immense cost of respinning a physical chip. Back-end engineers, often called Physical Design Engineers, take the verified RTL and turn it into a physical blueprint ready for manufacturing. This intricate process involves synthesis, which converts the RTL into a gate-level netlist, followed by floorplanning, where the chip's layout is strategically mapped out. They then perform placement and clock tree synthesis (CTS) to optimize timing and power distribution, and routing, which connects all the millions of transistors. Throughout this process, they must continuously analyze and fix challenges related to timing, power integrity (EM/IR), and signal integrity to meet all performance and reliability goals, culminating in a final GDSII file sent for fabrication. Typical responsibilities across these roles include collaborating with cross-functional teams including verification, architecture, and packaging; performing timing analysis; implementing design changes (ECOs); and running physical verification checks (DRC, LVS) to ensure the design is manufacturable. Professionals in this field are expected to have a strong foundation in digital logic design, computer architecture, and semiconductor physics. Proficiency with industry-standard EDA tools from vendors like Synopsys and Cadence is essential, as is experience with scripting languages like TCL, Perl, or Python to automate workflows. A bachelor's or master's degree in Electrical or Computer Engineering is a standard requirement, with senior positions demanding extensive experience and a proven track record of successful tape-outs, especially in advanced process nodes like 7nm and below. The search for ASIC Design Engineer jobs leads to a rewarding career for those who are detail-oriented, adept at problem-solving, and passionate about building the foundational technology of tomorrow. If you have a blend of creative engineering and analytical rigor, this profession offers a challenging and impactful path in shaping the future of electronics.

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