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Voltai seeks an RTL Design Engineer in Palo Alto with 5+ years of chip tape-out experience. Own SystemVerilog microarchitecture, drive synthesis and timing closure, and help evaluate AI-generated RTL.
Voltai seeks a Synthesis & STA Engineer in Palo Alto with 5+ years of tapeout experience. Own logic synthesis, SDC development, and timing closure using Design Compiler, PrimeTime, and Tcl/Python scripting.