Renesas Electronics - United States, Duluth, Engineering

Principal Analog Design Engineer in Duluth to architect and verify CMOS analog blocks for custom ASICs. Requires 10-15 years of analog design experience and DDR5/DDR6 I/O expertise.

Lead post-silicon validation for DDR5 memory buffers in Duluth. Requires 8+ years in high-speed analog/mixed-signal characterization, BERT/scope expertise, Python scripting, and strong signal integrity knowledge.

Lead post-silicon validation for DDR5 memory in Duluth. Requires 8+ years in high-speed analog/mixed-signal testing, BERT/scope expertise, Python scripting, and strong signal integrity knowledge. Drive silicon bring-up and debug.

Lead verification strategy for next-gen DDR6 semiconductor memory interfaces in Duluth. Requires deep SystemVerilog and UVM expertise, technical ownership of complex verification efforts, and collaboration with RTL design teams. DDR experience a plus.

Renesas seeks a Senior Staff Design Verification Engineer in Duluth to lead verification of advanced memory interface products for data center and AI. Requires 10+ years in semiconductor verification, SystemVerilog and UVM expertise.