Renesas Electronics - United States, Duluth

Principal Analog Design Engineer in Duluth to architect and verify CMOS analog blocks for custom ASICs. Requires 10-15 years of analog design experience and DDR5/DDR6 I/O expertise.

Renesas seeks an entry-level Electrical Engineer in Duluth, GA (hybrid) to verify DDR5/DDR6 memory interface chips for AI and cloud datacenters. Requires a BSc with up to 2 years experience or a recent master's grad.

Lead post-silicon validation for DDR5 memory buffers in Duluth. Requires 8+ years in high-speed analog/mixed-signal characterization, BERT/scope expertise, Python scripting, and strong signal integrity knowledge.

Entry-level Validation Engineer role in Duluth, GA for recent Master's graduates in EE or Computer Engineering. Hands-on silicon validation work with DDR, memory controllers, and lab equipment. Requires Python/C/C++ skills and strong circuit knowledge.

Experienced Principal Application Engineer needed in Duluth to validate DDR3/4/5 and SERDES memory interface products. Requires 10+ years in post-silicon validation, Python automation, and lab equipment expertise.

Join Renesas as a Design Verification Intern in Duluth, GA (hybrid) for Summer 2027. Work on cutting-edge DDR5/DDR6 memory buffer chips using Verilog, SystemVerilog and UVM. Enrolled students only.

Lead post-silicon validation for DDR5 memory in Duluth. Requires 8+ years in high-speed analog/mixed-signal testing, BERT/scope expertise, Python scripting, and strong signal integrity knowledge. Drive silicon bring-up and debug.

Lead verification strategy for next-gen DDR6 semiconductor memory interfaces in Duluth. Requires deep SystemVerilog and UVM expertise, technical ownership of complex verification efforts, and collaboration with RTL design teams. DDR experience a plus.

Renesas seeks a Principal Digital Design Engineer in Duluth to architect RTL for DDR5/DDR6 memory buffer chips powering AI and cloud data centers. Requires 12+ years of ASIC/IC design expertise and strong Verilog skills.

Renesas seeks a Senior Staff Design Verification Engineer in Duluth to lead verification of advanced memory interface products for data center and AI. Requires 10+ years in semiconductor verification, SystemVerilog and UVM expertise.

Renesas seeks a Staff Design Verification Engineer in Duluth to verify advanced DDR6 memory interface products for data center and AI. Requires 8+ years in semiconductor verification, strong SystemVerilog and UVM skills.