Renesas Electronics - United States, Chandler, Hybrid work

Renesas seeks a Principal ESD Engineer in Chandler to lead ESD methodology, custom IP development, and sign-off verification for FinFET SoCs and SerDes. Requires 10+ years of ESD design expertise and strong leadership skills.

Senior Staff Analog Engineer in Chandler to lead PMIC and mixed-signal architecture across the full lifecycle. Requires 8-10 years in power management, CMOS expertise, and proven technical leadership with strong mentoring skills.

Experienced Staff Mask Design Engineer needed in Chandler to lead analog and mixed-signal IC layout for automotive applications. Requires 8+ years of layout experience, advanced CMOS BCD expertise, and strong physical verification skills.

Lead verification strategy for next-gen DDR6 semiconductor memory interfaces in Chandler. Requires deep SystemVerilog and UVM expertise, technical ownership of complex verification efforts, and strong collaboration with RTL design teams.

Renesas seeks a Staff Verification Engineer in Chandler to verify mixed-signal automotive PMIC designs. Requires 12+ years of experience, RNM/AMS modeling, GLS flows, and ISO 26262 expertise.

Lead the architectural evolution of PMIC and mixed-signal products as a global technical authority in Chandler. Requires 12+ years in power management, CMOS expertise, and proven technical leadership on complex ICs.