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Globalfoundries - Taiwan

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Senior Engineer, ASIC Digital Design (System IP Verification)

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Senior ASIC Digital Design Engineer role in Hsinchu, Taiwan, verifying configurable system-level IP and subsystems for next-gen RISC-V platforms. Requires a Master's degree and hands-on Verilog/SystemVerilog, C/C++ or Python skills.
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Location
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Salary
Not provided
Globalfoundries
Expiration Date
Until further notice