Envision Employment Solutions - Engineering

Senior RTL Design Engineer to own complex SoC design from architecture to tapeout. Requires 7+ years VLSI experience, strong Verilog/SystemVerilog, lint, CDC and synthesis skills. Hands-on microarchitecture role with real impact.

Senior EDA/CAD Engineer to own full SoC EDA flows and CAD infrastructure, from Cadence, Synopsys and Siemens tools to Linux compute farms, licensing and CI/CD. Requires 7+ years of EDA/CAD experience, Python, Perl, Shell and Tcl scripting, plus AI tooling integration.

Lead DFT architecture for complex multi-die and chiplet SoCs, owning test access, ATPG and scan compression strategy. Requires 10+ years DFT experience, Tessent/Synopsys/Cadence tools and strong PD collaboration.

Senior Physical Design Engineer role focused on synthesis, SDC and STA for advanced nodes (10nm and below). Requires 10+ years of experience, strong Synopsys/Cadence tool skills, and proven RTL-to-GDSII tapeout record.

Lead physical architecture for SiP and chiplet designs, integrating dies, packaging, power, thermal and signal integrity into one system. Requires 10+ years in physical design/SoC architecture and hands-on SiP or advanced packaging experience.