Duo Security - On-site work

Lead ASIC Design Verification for Cisco’s cutting-edge Silicon Photonics and Co-packaged Optics (CPO) in Pune, India. Leverage 8-12 years of UVM, SystemVerilog, and Python expertise to verify 800G/1.6T transceivers. Drive block-to-SoC verification, debug complex RTL issues, and collaborate on pos...

Senior ASIC Design Verification Engineer sought by Cisco’s Common Hardware Group in Bangalore. Leverage 7+ years of UVM/System Verilog expertise to architect and build top-level DV environments for cutting-edge Cisco Silicon One ASICs. Drive verification from test bench creation to post-silicon b...

Join Cisco in Bangalore as a Senior Signal and Power Integrity Engineer. You will deliver SI/PI solutions for high-speed systems, utilizing tools like ADS and HFSS. This role requires 6+ years of experience with SerDes technologies (56G PAM4, DDR) and lab measurements. Collaborate with cross-func...