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Join Cisco's ASIC Physical Design Team in Yerevan, in a hybrid role. Drive full-chip implementation from RTL to GDSII, using Synopsys/Cadence tools for synthesis, PnR, and timing closure. Optimize for power, performance, and area (PPA) in a collaborative environment shaping future silicon. Requir...
Location
Armenia , Yerevan
Salary
Not provided
Expiration Date
Until further notice
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