Astera Labs - United States, San Jose, Engineering

Lead SerDes/PHY IP verification at Astera Labs in San Jose. Requires 8+ years in UVM/SystemVerilog, mixed-signal co-simulation, and high-speed protocols like PCIe or CXL. Architect verification for AI connectivity solutions.

Astera Labs seeks a Principal Electrical Design Engineer in San Jose to architect high-speed board-level hardware for AI infrastructure. Requires 12+ years in PCIe Gen5/6 and 400G/800G Ethernet design with strong signal integrity expertise.

Lead hardware board validation strategy at Astera Labs in San Jose. Requires 12-15+ years in high-speed board design, PCIe/CEM cards, and team leadership. Drive bring-up, debug, and production release for AI infrastructure.