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Countries
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This list contains only the countries for which job offers have been published in the selected language (e.g., in the French version, only job offers written in French are displayed, and in the English version, only those in English).
Join Astera Labs as a Principal Physical Design Engineer in Singapore. Lead block and top-level implementation in advanced nodes, drive timing closure, and integrate high-speed IPs. 5-10 years of experience required.
Lead Physical Design Engineer role at Astera Labs in Singapore. Requires 5+ years in physical design, advanced nodes, Synopsys ICC2/Cadence Innovus, and high-speed IP integration for AI infrastructure.
Lead Analog Mixed-Signal IC Layout at Astera Labs in Singapore. Requires VLSI/Computer Architecture background, Verilog/SystemVerilog, UVM and Python/C++ skills. Join the AI connectivity revolution!