Astera Labs - India, Engineering

Lead ASIC Design Verification role in Bengaluru requiring 6+ years of SoC/silicon verification experience. Drive block and system-level DV for PCIe/CXL protocols, develop test plans, and debug with RTL designers. Strong EE/CE background and VIP expertise needed.

Astera Labs seeks a Principal Physical Design Engineer in Ahmedabad to drive complex SoC/silicon development for AI infrastructure. Requires 8+ years of backend experience with 16nm or smaller technologies and strong EE background.